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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Introductory
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    A design methodology for sizing and determining delays in logic paths will be developed that will be used throughout the design cycle. One of the key items in sizing and optimizing the logic path is called fanout which will be the main focuses of this tutorial. We will first determine what fanout is and how it relates to the gain (output capacitance vs. input capacitance) of an inverter and a complete logic path. Then, a delay equation for calculating the delay through any logic path based on fanout will be created to aid in quickly calculating the initial timing and sizing of the logic gates. Timing and sizing calculations will always be related to an inverter, so we will review how to convert a NAND and NOR gate drive strength to an equivalent inverter to be used in the delay equation.

    A key question that will always arise throughout a design will be: what is the optimum fanout when we have a very small initial stage in a logic path that must eventually drive a large capacitance? In another words, how many gain stages should we use and what size should each stage be. To answer this, we will create a graph that will tell us the optimum fanout that we should always use and thus standardize the delay per stage. Standardizing fanout will eliminate many variations within our design and allow for all logic paths to track over process, temperature and voltage variations. This is a very important design methodology in improving the quality of our design and helping to insure that it works the first time.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

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    Author: Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Introductory
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    This tutorial will expand the analysis of delay and fanout to include the additional parasitic capacitance load that occurs from layout. A standardized method for converting capacitance to equivalent gate size will be presented, and the examples from Part 1 will be reworked to include parasitic capacitance. It is imperative that there be a good understanding of how layout causes parasitic capacitance which can greatly affect the performance and functionality of a design. We will evaluate this by first reviewing the basics of layout with substantial focus on the metal interconnect layers and the types of capacitance the various structures create. Finally, a simulation methodology will be presented for incorporating the actual extracted layout into SPICE for an accurate analysis of the design.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard ,Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    This tutorial walks you through the initial steps in designing an SRAM and then focuses on the first circuit that we must design the memory cell. An overview of the architecture will be presented in a block diagram that will describe the functions of the major blocks required to create an SRAM. A large portion of this video will be dedicated to the design and layout of the memory cell (also called the bit cell) and how it is arrayed. It starts with a description of how the memory cell works then analyzes how the cell is read and written, with specific attention paid to read disturb which can cause the cell to inadvertently flip when it is read. Waveforms from SPICE simulations of the memory cell will be presented along with a SPICE input file that can be used to create your own simulations. A SPICE netlist from the layout of the memory cell will also be supplied so that the actual parasitic capacitance can be included in the simulations.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    A chip plan of the layout will be created from the architecture and block diagram discussed in the previous tutorial. This chip plan leads to the next design steps of the array and the circuits that interface to it. A very accurate model of the memory array will be developed and put into SPICE for all of the future simulations. Array waveforms from actual SPICE simulations will be reviewed in detail with a focus on the precharge signal and the resulting precharge circuitry that must interface to the bitlines. Schematics of the precharge circuit will be presented along with a detailed discussion of the requirements and how it relates to the read cycle. Layout of the precharge circuit will be supplied along with a SPICE netlist that includes extracted parasitic capacitance from the layout.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3

    Abstract
    A good design approach is to first consider the read cycle by designing the read path from the memory cell all the way out to the Data Out Pad. This tutorial takes the small signal that the memory cell creates and focuses on the Sensing Scheme that is required to create the gain necessary to create a full CMOS level. The function and design of the Sense Amp will be discussed in detail as well as the key requirements of the various control signals, some of which have dual purposes such as controlling precharge and performing a 1 of 2 decode. There are many subtle things that must be considered and analyzed when designing the Sensing Scheme, not only in the schematics but in the layout as well. As such, portions of the layout will be reviewed along with an approach that eliminates noise that could cause it to fail. Plots of the layout will be provided along with an extracted SPICE netlist. Waveforms from the SPICE simulation will also be reviewed.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    This tutorial continues the design of the read path from the output of the sense amp through the Data Out Buffer into the data out driver and eventually to the pad that the customer connects to. The dual use of the sense amp clock signal is discussed whereby it creates an additional 1 of 2 decode that results in a mux factor of four. Other mux factors will be designed to allow for a reconfigurable memory. A new control signal called Output Enable will be discussed and will be designed into the Data Out Buffer for controlling how the SRAM drives the data out pad. As always, plots of the layout and an extracted SPICE netlist from layout will be included.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Nov-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The overall data path of a memory can be divided into two paths - the read path and the write path. This tutorial focuses on the write path of an SRAM. The write path has some unique requirements that the read path does not have, although there are some similarities as well. This design will include: the internal decoding for a write, the data in buffer and key control circuits along with their timing relationships. The overall integration of the write and read path will be designed thereby making up the complete data path into and out of the memory cell. A complete set of plots are provided along with a SPICE netlist that is extracted from the layout.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Dec-2009
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The access of a memory cell starts when the Word Line is asserted which is controlled by the Word Line Driver and the Row Decoder. This tutorial will focus on the design of the Row Decoder starting with an overview of a basic decoder, and then will describe a greatly improved version that is faster and presents a smaller load to the Address Buffers. The Word Line Driver will be designed such that it is controlled by an internal clock which is critical to the overall timing associated with reading and writing the memory cell. Additional enhancements to the Word Line Driver will be made to reduce the layout area so that it can fit in the small pitch of a memory cell and have increased performance.

    Keywords: Channel length , Fanout , digital circuit , integrated circuit , p-channel , transistor

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Feb-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The main function of the address buffer is to take the address presented by the customer, latch it and have enough gain to drive the large load presented by the Row and Column Decoders. It must also present a small load to the pin that connects to the customers addresses and meet stringent set up and hold requirements. This tutorial will describe how to design an address buffer that meets these specifications including the difficult task of achieving a 0ns hold time.

    Keywords: circuits , integrated circuts

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Mar-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The design is now entering into the timing relationships between the various circuits in the RAM and how they interact with each other. The Clock Buffer is where it all starts and, as such, is critical in designing the timing throughout the RAM. A very special function of the Clock Buffer is to capture the rising edge of Clock and then create the key internal clock that will be self-timed and not dependent on the falling edge of Clock. This is the first step in designing the control circuitry that creates the various signals that control all aspects of the RAM.

    Keywords: circuits , integrated circuts

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: April-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The previous tutorials in this series focused on the design of individual circuits. Now we begin putting it all together. This tutorial will focus on the interaction between the circuits and their key timing relationships by comparing the individual timing paths. The control circuit will be designed to create: global signals for activating the word lines, passing and latching the address, set-up time, hold time, enabling and disabling pre-charge, read select timing and write select timing. Adhering to a fanout of 4 will greatly aid in quickly evaluating each timing path without initially needing to run SPICE simulations.

    Keywords: control circuit , global signals , integrated circuits , timing paths

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: July-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    This tutorial completes the design of the control circuits and focuses on controlling the Sense Amp and enabling the write data. An additional requirement for decoding which columns are written to and read from will be achieved through column decode circuitry that determines which SACL(3:0) and WCRWT(3:0) will be selected. One of the key features of the design will focus on Bit Line Ref (BLRF) which indicates when acceptable differential has been created at the input to the Sense Amp. This indicator is designed to tract the actual memory cell’s driving of the bit lines in a way that can adjust the timing of SACL based on variations in process, conditions and changes in the drive strength of the accessed memory cell.

    Keywords: communications, 3G , wireless

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

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    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Oct-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    This is the final tutorial in the series of tutorials on the Single Port SRAM design, and is the final step in the full circuit analysis that was done by a design engineer before the design was built in the fab. There are many subtleties to be considered when running full circuit simulations on memories with the main goal of analyzing the weakest portions of the design and evaluating how much margin there is under worst case situations. Combinations of cycles must be considered to determine how a previous cycle can affect the quality of the next cycle. Location of the memory cell accessed in the old and new cycle, old data vs. new data, write cycle effects on the next read cycle are all evaluated in this tutorial. Results of SPICE simulations and waveforms will be presented along with discussion of the top level simulation schematic that must accurately model the loading by all cells on signal nodes in the layout.

    Keywords: SRAM , circuits and devices , digital circuits

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.