• Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: January-2014
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    Since there are 2 ports in this design, there must be 2 Row Decoders – one for each port. A big portion of the challenge is to be able to lay out the both Row Decoders and have each one be able to interface with every row of bit cells. I addition to that, the inputs to from the address buffers associated with each port must be considered in how they are placed in the layout.

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.


  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: March-2012
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The influence that one port can have on the other port bit line can be a subtle, yet costly problem if not fully evaluated, and can in fact result in the design not working. Capacitive coupling between neighboring bit lines must be properly modeled and evaluated to determine their impact based on the different conditions that can occur in a dual port. This tutorial evaluates the worst case circumstances that can cause the differential during a read to be degraded - such as writing from one port while reading from the other, data dependency and bit cell location.

    Keywords: bit line, dual port, SRAM

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: December-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    There are several important timings that must be considered when designing the Data In Buffer that go beyond amplifying the input signal to drive the data to be written into the bit cell. The control timing must be such that the hold time for data in from the customer can be zero and not cause a change on the pin to propagate all the way to the bit cell and disturb what was just written. This tutorial makes a deeper evaluation of the timing paths that must be considered between clock and data in.

    Keywords: Integrated circuits , data input , data input buffer

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Dec-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


    Abstract
    This is the first in a series of tutorials on the design of a dual port SRAM. In this first tutorial an overview of the dual port SRAM is presented and compared to the single port SRAM. The benefits of a dual port at the system level are discussed followed by more details at the chip level which includes block diagrams and chip plans. The special requirements for the two independent ports accessing the shared memory array are reviewed in detail along with the operation of the dual port memory cell.

    Keywords: Array , Bit Line (BL) , FIFO (First In First Out) , Pass Gate , Pre-charge , Word Line (WL)

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Dec-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    AbstractThere are many more interactions that must be considered when designing a Dual Port memory as compared to a Single Port memory, especially since each port is completely independent of the other. This tutorial focuses on reading and writing the memory cell and how the actions of the other port can have major effects on what occurs in the cell. One of the key types of conditions that must be analyzed when calculating the beta ratio of the cell is called a collision, where both ports access the same memory cell at the same time. Several comparisons will be made to the Single Port SRAM to better examine the issues associated with the Dual Port.

    Keywords: Array , Bit Line (BL) , FIFO (First In First Out) , Pass Gate , Pre-charge , Word Line (WL)

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.
  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Dec-2010
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


    Abstract
    Analyzing the types of conditions that can cause capacitive coupling between bit lines in a memory array is very critical in assuring that the data from the memory cell will be properly read. The state and location of one memory cell relative to others can influence the voltage level that is being sensed. This is made even more complex in the case of a dual port where what is occurring on one port can effect what is occurring on the other port. Interactions between reading one port while writing the other must also be considered. The types of capacitance that can occur from layout is reviewed in this tutorial which focuses on the impact that the layout design of the memory cell has on bit line coupling under several of the conditions mentioned above. An actual layout of a dual port memory cell will be provided in PDF and trade offs in the design will be discussed.

    Keywords: Bitline , Capacitance coupling , Side-to-Side coupling capacitance , integrated circuits

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: May-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the memory cell array in rows and columns which in turn will determine the column decode and row decode scheme. In the case of a dual port there are 2 sets of column decoders and 2 sets of row decoders – one for each port. The column decode must be chosen such that it selects the appropriate number of columns within the array that will result in the required bits per word (BPW) that the customer requires. This tutorial presents various array configurations and the relationship between the total bits, bits per word, number of rows and number of columns.

    Keywords: Bits Per Word , Column Address , Data In , Data Out , Mux Factor , Row address

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: May-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    In memory design it is vitally important that the array be modeled in SPICE very accurately. This is required for proper analysis of: design margin, timing, performance, power and overall characterization of the design. Since a memory can have millions of memory cells (bit cells) it is unpractical to include every cell in the SPICE simulation as it would be too large and make the simulation time very long. This tutorial presents a method of modeling the array loading of the bit lines and word lines utilizing the mult factor in SPICE without compromising the accuracy of the simulation. The overall architecture of the chip layout is analyzed to determine the best approach for the particular configuration of the memory.

    Keywords: .Param , Backend , Bits Per Word , Data in , Mult Factor , data Out

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: June-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of rows and columns in the array. All of the key blocks required to decode the columns, sense the data, select and decode the sense amp and drive the Data Out pin for a read from the bit lines are discussed. The write path from the Data In pin up through the column decode and write select circuitry is also presented.

    Keywords: 1/8 Column Decode , Data Slice , Pitched Circuitry , Pre-charge , Sense Amp Clock

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: June-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the customer must meet will first be reviewed with a specific focus on the clock cycle. The key internal signals of the word line and the pre-charging of the bit lines and their relationship will be discussed along with the pre-charge circuitry. The timing interaction and relationships between the 2 ports must be kept in mind.

    Keywords: Synchronous , pre-charge , read-collision

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Sept-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract

    This tutorial follows the read path from the word line to the input of the sense amp which includes the initial column decode that selects the appropriate bit line. Particular attention will be paid to the large capacitive load that the memory cells have on the bit lines, and waveforms from simulations will be shown that indicate how slow their transition is. The initial conditions for both the bit lines and the input to the sense amp is also discussed. The circuitry for the pre-charging of the bit lines and the sense amp will be reviewed along with read select circuitry.

    Keywords: integrated circuits , read-path , sense amp

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Sept-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial.

    Keywords: SRAM , integrated circuits , sensing scheme

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: Sept-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


    Abstract

    There are several important features required for how the data output is controlled and how it drives the data out pin that the customer connects to. This Dual Port tutorial describes the design of the Data Output Buffer and how it is used to latch the data out and hold it valid even into the next cycle. Special pre-charge functions are designed into the buffer to allow for easy ripple thru of data to the output once the sense amp asserts but still will latch and hold the data after it goes back into pre-charge. The design of other features such as the use of OEZ to control when the output is in high Z is discussed. Schematics and waveforms from SPICE simulations will be presented, and the complete read path from when the word line asserts to the output of data at the pin will be evaluated.

    Keywords: Integrated circuits , data output , data output buffer

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: October-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The interaction in the array between the two ports can have some adverse effects that must be evaluated when designing a Dual Port SRAM, especially when one of the ports is doing a write. This tutorial takes a close look at a "Word Line collision" that occurs when one port is writing while the other port is reading the same row. SPICE simulation waveforms will be evaluated showing the interaction that can occur through the bit cell and affect what happens on the bit lines between the two ports. The situation where both ports access the same bit cell while one port is reading and the other port is writing is also evaluated.

    Keywords: Integrated circuits , SPICE , SRAM

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

  • Access Now

    Author:Sheppard, Douglas
    Sponsored by: IEEE Educational Activities Department
    Tutorial Level: Intermediate
    Publication Date: October-2011
    Run Time: 1:00:00
    CEUs: .3
    PDHs: 3
    ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

    Abstract
    The circuits in the write path from the bit cell through the write drivers and down to the write select circuitry are discussed. Specific analysis is done with one port writing while the other port is reading from the same row. The decoding approach for determining which bit line is driven low for a write is compared to the decoding required for reading the selected bit line and passing it out to the data out pin. Timing relationships between the key signals for doing a write will be evaluated from SPICE simulations.

    Keywords: Integrated circuits , bit cell , write path

    For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.