Access Now

Author: Tsakalakos, Loucas
Sponsored by: IEEE Educational Activities
Tutorial Level: Intermediate
Publication Date: June-2012
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract

In this tutorial Dr. Tsakalakos discusses the fabrication of nanostructures using both top-down and bottom-up approaches. Methods for fabricating zero-dimensional, one-dimensional and two-dimensional nanostructures are also presented. Dr. Tsakalakos reviews the process for creating carbon fullerenes and nanotubes. The various types of lithography used to create nanostructures and the self-assembly of nanostructures are presented. Different properties (structural, chemical, mechanical, optical, electronic) of nanostructures can be analyzed using various approaches. Finally some of the many uses for nanostructures are listed.

Key words: nanostructure, nanofabrication

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Apolloni, Bruno; Muscato, Orazio; and Rinaudo, Salvatore
Sponsored by: ST Microelectronics
Tutorial Level: Introductory
Publication Date: Sept-2010
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
Cost control, production efficiency, cycle time and yield are critical quality benchmarks for nano-electronics production. Their sensitivity to the statistical variations of the IC manufacturing process is increasing more and more in comparison to the process complexity. Therefore, the following two joint tasks become essential:

• To characterize statistically IC manufacturing fluctuations,
• To predict reliably circuit performance spreads at the design stage.

In this tutorial we will introduce yield concept in electronic design; get acquainted with mathematical issues; review methodologies in order to face the problem, their classification and type; and introduce a new methodology to improve computation of yield optimization.

Keywords: IC Circuits , production efficiency

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Robertson, David
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Introductory
Publication Date: Nov-2010
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial will cover the principles and architectures of analog digital converter design. The tutorial begins with a review of domain conversion including sampling, aliasing, and usable bandwidth. Next, quantization will be discussed with a focus on effective dynamic range and linearity. The tutorial will conclude with a review of architectural survey including single slope/dual slope ADCs, flash ADCs, successive approximation, algorithmic ADCs, pipeline ADCs, sigma delta modulators and continuous time sigma delta.

Keywords: ADCs , architecture , time sigma delta

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Robertson, David
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Introductory
Publication Date: Nov-2010
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial will cover the ADC building blocks and design trade-offs of analog digital converter design. The tutorial begins by discussing handling signals including voltage, current and charge. Next, signal management (“floors and ceilings”) will be covered. This will lead into a discussion of the key building blocks: Comparator, Amplifiers, SHA, and DAC.

Keywords: ADCs , architecture , time sigma delta

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Roska, Tamas
Sponsored by:IEEE Circuits & Systems Society
Tutorial Level: Intermediate
Publication Date: Jul-2009
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


Abstract
The cellular wave computer architecture, based on the CNN universal machine principle, has been implemented recently in many different physical forms. The mixed mode CMOS, the emulated digital (cell wise or as aggregated arrays), FPGA, DSP, as well as optical implementations are the main examples. In many cases, the sensory array is integrated as well.

This course will begin with an introduction that provides a historical overview. The author then presents mind inspired and brain inspired computing models, the role of spatial address of a processor, and new directions and products in computing the technology scenario. Other topics that will be addressed include:

*The Cellular Wave Computer
*The Cell Processors
*The Biology Relevance
*The Algorithmic Scenario
*Beyond Boolean logic

Keywords: cell processor , cellular active wave algorithm , cellular computer architecture , cellular many-core chip , cellular supercomputers , cellular visual microprocessor , cellular wave computer , morphic computing/processing , signal flow , wave instruction

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Taur, Yuan
Sponsored by:IEEE Electron Devices Society
Tutorial Level: Intermediate
Publication Date: Dec-2004
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

AbstractBeginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm; this tutorial examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy; tunneling leakage through gate oxide; and 2D electrostatic scale length. Both the standby power and the active power of a processor chip will increase precipitously below the 0.1-µm or 100-nm technology generation. To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented. It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile. Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm.

Keywords: CMOS , FinFET , High k , QM , halo , kT , scale length , subthreshold , tunneling , volume inversion

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Ho, Ron
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Intermediate
Publication Date: Dec-2008
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial discusses on-chip wires, how to model them, what are their problems (and their advantages) and some solutions. Topics that will be covered include: wire characteristics and how they determine performance; wires under technology scaling; and methods to improve wire performance.

Keywords: Fanout-of-four inverter delay (FO4) , Low-K dielectrics , elmore delay , equalization , global wires , local wires , partial inductance , repeaters , transmission lines , wire , wire capacitance , wire inductance , wire resistance

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Moschytz, George
Sponsored by:IEEE Circuits & Systems Society
Tutorial Level: Introductory/intermediate
Publication Date: Feb-2008
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
The concept of the 'Analog Front End' (AFE), which is the interface to the real world in most IC-system chips, is first introduced. The course then focuses on active-RC filters which constitute an essential part of most AFEs. The formulation of filter specifications and the basic ideas associated with classical filter approximation theory are then briefly reviewed. Some key points of classical network theory, as needed for the understanding of inductorless filter design, are then briefly recalled. This is followed by some basic concepts of signal-flow graph theory, which permit the transition from transfer function (resulting from approximation theory) to circuit topology.

After the review of these introductory and basic concepts, the stage is set to consider some of the most important and established active-RC filter-design techniques. Examples are given for the conversion of classical LCR filter structures into inductorless active-RC filter circuits that are amenable to IC chip design. The examples are taken from typical modern communication systems. Finally, filters designed using the design techniques covered in the course are compared in terms of practical performance criteria such as thermal output noise, sensitivity to component tolerances, and tunablity.

Keywords: Frequency-Dependent Negative Resistor , Mixed-Mode Signal Processing/IC Design , Transfer Function , VLSI , analog front end , analog signal processing , biquadratic (second-order) filter building block , capacitor , complex-frequency plane , digital signal processing

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Ellis, Wayne
Sponsored by:IEEE Reliability Society
Tutorial Level: Intermediate
Publication Date: Nov-2004
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to activate latent defects and screen out those chips that cannot meet product specifications for performance, power, and operating margins. The advent of degraded VLSI circuit operating margins due to the activated defects as well as reliability mechanisms such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and others will be discussed. How these failing circuits can then manifest themselves in observed product failures will also be discussed.

Keywords: Application Specific Integrated Circuit (ASIC) , Dynamic Random Access Memory (DRAM) , Static Random Access Memory (SRAM) , Very Large Scale , burn in , critical area , defect , destructive read , failure analysis , logic circuit , redundancy , reliability mechanism

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Yanduru, Naveen
Sponsored by: IEEE Microwave Theory & Techniques Society
Tutorial Level: Introductory
Publication Date: Aug-2009
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
Various RF bands, standards, modulation schemes, duplex mechanisms and signal bandwidths needed for the mobile terminal call for a highly adaptable and reconfigurable RF receiver. The biggest bottleneck in achieving this goal lies with the RF pre-select filter at the antenna, which is band specific and creates a bottleneck in being able to share the hardware. Solving this "multi-band" programmability is the biggest challenge in achieving a RF Receiver for software defined radio. A few of the possible architectures and their limitations are presented. However, designing a "multi-mode" RF receiver for a given RF band with highly reconfigurable performance is an achievable goal. A WCDMA/EDGE receiver without inter-stage SAW filter in 90nm digital CMOS is used as an example in illustrating the architecture, circuit and system considerations for such a receiver.

Keywords: Amplitude Modulation , Continuous Wave (single tone) , Dedicated Physical Channel , Enhanced Data GSM Environment , Frequency Division Duplex , Global System for Mobile communications , Inter Modulation , Local Oscillator , Low Noise Amplifier , Peak to Average Ratio

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Gambino, Jeff
Sponsored by:IEEE Electron Devices Society
Tutorial Level: Intermediate
Publication Date: Nov-2008
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial will provide an overview of advanced interconnect technologies, including dielectric materials, patterning, metallization, CMP, and packaging. New processes will be discussed, such as ultra-low K dielectrics, air-gap structures, low-damage patterning methods, thin barrier and seed layers, refractory metal capping layers, and novel CMP techniques. The effect of these processes on performance and reliability will be briefly described.

Keywords: Barrier layers , Diffusion barriers , Dual damascene , Electroplating , Low-k dielectric , Technology node , Ultra low-k dielectric , chemical mechanical polishing , insulator , lithographic dimension , physical vapor deposition , plasma enhanced chemical vapor deposition , reactive ion etching , wafer

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Authors:Schmalzel, John L.andFowler, Kim
Sponsored by:IEEE Instrumentation & Measurement Society
Tutorial Level: Introductory
Publication Date: Apr-2005
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

AbstractThis tutorial discusses how measurement is a key to life and explores where we use measurements. It defines instrumentation and measurement and reviews basic principles. Case studies detail car, LOX tank, submarine data acquisition system, and medical device examples. This tutorial also explores where instrumentation is found (e.g. laboratory, field instruments, car engine control, aircraft avionics and flight control, bridges, factories, houses, appliances) and discuss systems of instruments. It reviews sensor types, sizes, and systems and covers basic instrumentation with a look at general configurations focused on areas such as inputs, conditioning and transformation, analog pre-processing, analog-to-digital converters (ADCs), outputs and basic processing. Review system configurations and the evolution of system designs are also discussed.

Keywords: accuracy , calibration , full scale output , hysteresis , instrumentation , linearity , measurand , measurement , noise , precision , resolution , sa , sensitivity , sensor , span or range , specificity , stability , survivability , threshold , transducer , transfer function

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Meyyappan, Meyya
Sponsored by:IEEE Educational Activities
Tutorial Level: Introductory
Publication Date: Dec-2009
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This course introduces the subject of nanotechnology to the beginner. Nanotechnolgoy will be defined and different nanomaterials will be presented. This course will explain what is special about nanotechology and why nanoproperties are different from bulk properties. Several examples will be presented that will examine the impact of nanotechnology on each economic sector.

Keywords: nanoproperties , nanotechnology

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Rohrer, Norman
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Introductory/Intermediate
Publication Date: Feb-2007
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
Variability is a reality in nanometer semiconductor processes. This course will cover the sources of systematic and random variations of transistors and their surrounding interconnects. Included in the variability discussion will be within-chip variability, across-wafer variability, across-device variability, and device mismatch. The resulting impact upon an individual circuit’s functionality and timing will be explored. Analytical approaches will be shown for examining the variability’s impact upon leakage power, dynamic power, and circuit functionality of static and dynamic circuits, SRAM arrays and PLLs. Techniques will include Monte-Carlo analysis, vector analysis, and statistical timing analysis.

Keywords: Analysis , Beta Ratio , Instability , Line Edge Roughness , Monte Carlo , NBTI , Negative Bias Temperature , Random Variation , Random dopant fluctuation , Systematic Variation , Temporal Variation , Worst Case Vector

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Richter, Curt
Sponsored by:IEEE Electron Devices Society , IEEE Reliability Society
Tutorial Level: Introductory
Publication Date: Aug-2007
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This course will begin by outlining approaching limits of conventional CMOS technology. New architectural requirements and paradigms for future nanoelectronics will be described. ‘Top-down’ and ‘bottom-up’ manufacturing paradigms--particularly self-assembly of organic monolayers will be discussed. Theoretical and experimental realizations of molecular-scale electronic switches will be described. This course will also show nanoscale memory and logic circuits built with these materials and methods and will discuss potential nanoscale chemical and biological sensors built with these materials and methods.

Keywords: CT complex , Charge Transfer Complex , Dielectric , Isocyanide , Langmuir-Blodgett film , METS , Molecular Electronics , Molecular Electronics Test Structure , Monolayer , Nanopore , SAMs , Self assembled monolayers , Synthesis , electrical insulator , moletronics

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Stewart, Duncan
Sponsored by:IEEE Electron Devices Society , IEEE Reliability Society
Tutorial Level: Introductory
Publication Date: Jan-2008
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This is a two-part course. Part 2 titled “Molecular Electronics-II: Molecular Electronic Device Fabrication and Characterization” will:

• Discuss the advantages of molecular electronic devices and present experimental proof of concepts
• Describe the formation of molecular junctions, the central component of molecular electronic devices
• Describe the design and fabrication approaches for some of the most successful molecular electronic device prototypes
• Present electrical characterization approaches and challenges
• Discuss non-device based electrical screening approaches
• Present the current status and outlook for molecular electronic devices.

Keywords: Integrated circuit , METS , Molecular Electronics , Molecular Electronics Test Structure , Molecular switch , Monolayer , Moore's Law , Organic electronics , electronic circuits , moletronics

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Meyyappan, Meyya
Sponsored by:IEEE Educational Activities
Tutorial Level: Intermediate
Publication Date: Nov-2009
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This intermediate/advanced course discusses various nanomaterials such as carbon nanotubes, inorganic nanowires, dendrimers, nanoparticles, etc. In each case, the most successful approaches to prepare them are introduced. The focus will be on applications in sensors, instrumentation, electronics, etc. along with the potential to introduce them in respective industries.

Keywords: carbon , nanoproperties , nanotechnology , nanowires , sensors

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Wong, H.S. Phillip
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Introductory
Publication Date: Oct-2006
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial is an introduction to the emerging opportunities in novel nanoscale devices and fabrication techniques, with particular emphasis on the implications for circuit and system designers. Topics covered include:

• Fundamentals of device physics and materials science at the nanoscale
• The ITRS Emerging Research Devices (memory & logic)
• Nanotubes, nanowires, and nanoparticles
• Molecular devices
• Nanofabrication techniques and their impact on device layout

An assessment of the level of maturity for the proposed devices will be given. Part I provides an introduction, outlines key challenges, and covers ITRS emerging research devices, nanotubes, and nanowires.

Keywords: Buckyball , CMOS , Carbon Nanotubes , Complementary Metal Oxide Semiconductor , Molecular electronics , Molecular nanotechnology , Nano , Nanoelectromechanics (NEMS) , Nanoelectronics , Nanotechnology , Nanowire , Quantum dot , Self-Assembly , buckminsterfullerene , carbon , fullerenes

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Wong, H.S. Phillip
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Introductory
Publication Date: Oct-2006
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial is an introduction to the emerging opportunities in novel nanoscale devices and fabrication techniques, with particular emphasis on the implications for circuit and system designers. Topics covered include:

• Fundamentals of device physics and materials science at the nanoscale
• The ITRS Emerging Research Devices (memory & logic)
• Nanotubes, nanowires, and nanoparticles
• Molecular devices
• Nanofabrication techniques and their impact on device layout
  

An assessment of the level of maturity for the proposed devices will be given. Part II covers molecular electronics, emerging research memory devices, resistivity switching, nano for Si technology, and layout restrictions.

Keywords: Buckyball , CMOS , Carbon Nanotubes , Complementary Metal Oxide Semiconductor , Molecular electronics , Molecular nanotechnology , Nano , Nanoelectromechanics (NEMS) , Nanoelectronics , Nanotechnology , Nanowire , Quantum dot , Self-Assembly , buckminsterfullerene , carbon , fullerenes

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author: Tsakalakos, Loucas
Sponsored by:IEEE Educational Activities
Tutorial Level: Intermediate
Publication Date: April-2012
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract

Nanotechnology is concerned with the science and engineering of materials and devices at the sub-100 nm lengths. At the nanoscalethe properties of materials change from bulk values and behavior towards those of atoms, resulting in unique thermal, mechanical, electrical, and optical phenomena.
Specific subtopics addressed in this course are: carbon nanotubes, nanowires, self-assembled monolayers, plasmonics (nanoshells), quantum dots, core-shell nanoparticles, nanobiosensors, nanomedicine/drug delivery, and molecular machines. Many applications of nanotechnology are considered, including in electronics, textiles, energy, structural materials, biomedical, and other applications.

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Kymissis, Ioannis
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Advanced
Publication Date: Dec-2006
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
The tutorial will explain the theory underlying OFET operation, discuss practical fabrication strategies in use and underdevelopment, and discuss characterization and simulation of these devices, as well as some simple circuit implications considering their performance strengths and limitations.

Keywords: Conjugated , Hybridization , Molecular orbitals , Parylene , Pentacene , Polaron; Exciton , SAM , Self assembled monolayer , atomic orbital states , electron orbitals , neutral polaron , semiconductor

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Fischette, Dennis
Sponsored by:IEEE Solid-State Circuits Society
Tutorial Level: Intermediate
Publication Date: Jan-2005
Run Time: 1:40:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


Abstract
This tutorial provides a practical introduction to PLL design for clock synthesis. The twin goals of the tutorial are to provide practical advice on solving real-world PLL problems and to help develop an intuitive feel for PLL theory in order to prevent common design mistakes. This tutorial includes basic feedback loop theory and common circuit implementations, with emphasis on typical problem spots. It also focuses on design for test and debug, an important but often overlooked topic.

Keywords: bode plot , control voltage , damping factor , integral path , loop delay time constant , loop filter , phase tracking , phase-locked loop , thermal noise , transfer function

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Crowder, Scott
Sponsored by:IEEE Electron Devices Society
Tutorial Level: intermediate
Publication Date: Apr-2007
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial will discuss the requirements and transistor design issues in current and future low power technologies. After reviewing the trade-offs between low standby and low active power the methods for and required future innovations in low power process and transistor design will be discussed.

Keywords: Body Effect , DIBL , Drain Induced Barrier Lowering , Gate Length , High-K dielectrics , Inversion Capacitance , Mobility , SRAM , Static random access memory , Threshold Voltage , Workfunction , eDRAM , embedded DRAM

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Burger, Wayne
Sponsored by:IEEE Microwave Theory & Techniques Society
Tutorial Level: Intermediate
Publication Date: Dec-2009
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial begins by providing a review of recent advances in RF-LDMOS device technology (i.e. high power plastic packaging, higher efficiency, higher frequency capability, high power RFICs, 50V RF-LDMOS, etc.). Next, the tutorial will provide a comparison of various figures of merit of 28V and 50V RF-LDMOS with GaN, an emerging RF power technology that is attractive from several perspectives as an RF power device technology.

Keywords: ISM , Predistortion , RF , SMPA , nanotechnology , radio frequency

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Burghartz, Joachim N.
Sponsored by:IEEE Electron Devices Society
Tutorial Level: Introductory
Publication Date: Jun-2008
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


Abstract
In typical radio-frequency (RF) front-end circuits, the passive components outnumber the active devices. They occupy a major fraction of the total circuit area, and their low quality factor (Q) limits the circuit performance. Furthermore, these (intended) passive components can easily be perturbed by the interconnects feeding into them and coupled together by the (unintended) magnetic fields around those interconnects, or by (unintended) capacitive currents through the silicon substrate. One therefore needs to cope with both the optimization of the passive components, as far as Q and chip area consumption go, and the minimization of the crosstalk effects. This tutorial illustrates the design principles that lead to optimized integrated passive components on the basis of maximum Q and optimum RF isolation. Taking the well-established hybrid RF systems on printed circuit board (PCB) as a reference, the most commonly used passive components are discussed, and RF isolation techniques at chip and package level are explained.

Keywords: RF ICs , capacitive substrate currents , coupling , crosstalk , eddy currents , equivalent circuit models , ferromagnetics , loss , microwave integrated circuits , passive components , periodic structures , quality factor , self-resonance , skin effect , transmission lines

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Cressler, John D.
Sponsored by:IEEE Electron Devices Society
Tutorial Level: Intermediate/advanced
Publication Date: Feb-2005
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


Abstract
The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is the first practical bandgap-engineered device to be realized in silicon. This course will provide a comprehensive review of the state-of-the-art in SiGe HBTs and assess its potential for current and future wireless and wireline applications. SiGe HBT technology combines transistor performance competitive with III-V technologies such as GaAs and InP with the processing maturity, integration levels, yield, and cost commonly associated with conventional Si CMOS fabrication. First-generation SiGe HBTs can deliver: fT in excess of 50 GHz, fmax in excess of 70 GHz, minimum noise figure below 0.5 dB at 2.0 GHz, linearity efficiency (OIP3/Pdc) above 10, 1/f noise corner frequencies below 1 kHz, operation at cryogenic temperatures, excellent radiation hardness, as well as yield, reliability and cost comparable to Si. Aggressively-scaled SiGe HBTs can achieve greater than 200 GHz transistor-level performance, and thus are expected to enable Si-based solutions for >40 GB/sec data links and emerging RF, microwave, and even mm-wave systems.

Keywords: 1/f noise , IIP3 , Nfmin , Silicon-Germanium (SiGe) , bandgap engineering , cryogenic temperatures , epitaxy , heterojunction , radiation , system-on-a-chip (SoC)

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Temes, Gabor
Sponsored by:IEEE Circuits & Systems Society
Tutorial Level: Introductory
Publication Date: May-2007
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This course provides a clear understanding of the principles of delta-sigma data converter operation—analog to digital and digital to analog. It introduces the best computer-aided analysis and design techniques available. The course uses simplified methods to illustrate complicated concepts such as spectral estimation and switched noise.

Keywords: Delta-Sigma ADC , Delta-Sigma DAC , Delta-Sigma Modulator , Dither , Dynamic Element Matching , Idle Tones , Limit Cycles , MASH , Multi-Stage Noise Shaping Modulator , Noise Shaping , Oversampling , Unit Elements of a DAC

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Dayaratna, Lama
Sponsored by:IEEE Microwave Theory & Techniques Society
Tutorial Level: Introductory
Publication Date: Mar-2009
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time


Abstract
The objective of this course is to provide a state of the art review of phase locked loop circuits and applications from a design and development perspective. Intended for RF and Microwave Engineers, the course details out the design and development of phase locked loop circuits. Topics include PLL basics, VCOs, phase detectors, open and close loop characterization, loop filter design, and phase noise concepts. Examples will be given to a variety of problems relevant to the design of phase locked loops.

Keywords: Gain Margin , Integrated Circuit , Loop Filter , Loop Gain , Op Amp , Operational Amplifier , Phase Detector , Phase Margin , phase locked loop , radian

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Buus, Jens
Sponsored by:IEEE Photonics Society
Tutorial Level: Introductory
Publication Date: Feb-2006
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial describes the state-of-the-art of tunable lasers, tunable laser technologies, and control of tunable lasers. It also includes a brief introduction to the basics of semiconductor lasers, as well as background on DFB lasers, in particular how a grating works as a wavelength selective element in DFB and DBR lasers. Tuning mechanisms and tuning properties will be described and the operation of modified structures with extended tuning range will be explained, including sampled gratings and super structure gratings. The properties of co-directional couplers and the use of these in tunable lasers will be discussed. Devices such as external cavity lasers, wavelength selectable lasers, and tunable VCSELs, will also be described. Throughout the course numerous examples of laser structures from the recent technical literature will be presented. Practical issues such as characterization, operation, and control of tunable lasers, as well as switching speed and reliability, will be included.

Keywords: Fabry-Perot (FP) , International Telecommunications Union (ITU) , acousto-optical tunable filter (AOTF) , antireflection (AR) , dense WDM (DWDM) , distributed Bragg reflector (DBR) , distributed feedback (DFB) , electroabsorption modulator (EAM) , external cavity laser (ECL) , forward error correction (FEC)

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Deutsch, Alina
Sponsored by:IEEE Educational Activities Department
Tutorial Level: Introductory/Intermediate
Publication Date: Oct-2006
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial reviews the present-day on-chip wiring design practices and the special characteristics of on-chip lossy transmission lines. The deficiencies of present-day RC-circuit-representation-based designs and tools are highlighted through relevant examples. Guidelines are given for how to use controlled transmission line structures. Design practices are discussed for optimizing the wiring structure along with design methodologies to circumvent the negative effects of transmission line properties and best utilize these in the framework of improved technological advances. CAD tool development needs are explained for wire-aware chip architecture and for migrating to performance-driven routers and layout with R(f)L(f)C interconnect representation. The large, integrated chips that include major portions of the overall system are inheriting all the problems that package designers have faced for many years. It is explained how the system-on-chip concept needs to adopt and adapt the tools, understanding, and practices used for designing chip-to-chip interconnections.

Keywords: Bandwidth , CMOS , Coupled Noise , Critical net , Crosstalk , Data bus , Hierarchical cross section , Low K , SoC , Transmission Line , complementary metal oxide semiconductor , system-on-chip

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.

Access Now

Author:Deutsch, Alina
Sponsored by:IEEE Educational Activities Department
Tutorial Level: Introductory
Publication Date: Oct-2006
Run Time: 1:00:00
CEUs: .3
PDHs: 3
ECSA CPD (Category 1 - Development Activities): 1 - Includes study time

Abstract
This tutorial delves further into the present-day on-chip wiring design practices and the special characteristics of on-chip lossy transmission lines. A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties and the interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections.

Keywords: Bandwidth , CMOS , Coupled Noise , Critical net , Crosstalk , Data bus , Hierarchical cross section , Low K , SoC , Transmission Line , complementary metal oxide semiconductor , system-on-chip

For individuals not subscribed to the IEEE eLearning Library, this course is available for individual purchase.