Analog Circuit Design in Deep Sub-Micron CMOS Processes

Author / Presenter: Eric Soenen, Texas Instruments
Publication Year: 2004

Abstract: This presentation reviews some challenges of deep-sub micron analog design. While digital circuits benefit greatly from the high tranconductance of short-channel MOS transistors, analog circuits are limited by lower voltage gains, higher gate capacitance, and even gate leakage. The low supply voltages of the core transistors often necessitate specialized design techniques. One solution is to use a combination of low voltage core transistors and higher voltage I/O transistors.

Originally presented during the 2004 ISSCC Short Course, "Deep Submicron Analog/RF Circuit Design"
Presentations from this short course include:

• Models for Deep Sub-Micron Analog/Mixed-Signal ICs: 2004 ISSCC Short Course Segment
• Analog Circuit Design in Deep Sub-Micron CMOS Processes: 2004 ISSCC short Course Segment
• Recent Developments in RF CMOS Transceivers: 2004 ISSCC Short Course Segment
• Analog/RF Design in SiGe BiCMOS: 2004 ISSCC Short Course Segment

Author Bio: Eric Soenen received the Ph.D. degree from Texas A&M University in 1992, and an MBA from the University of Texas in 2000. He joined Texas Instruments in 1991. He was Design Manager for Data Converters and Product Line Manager for Wireless Infrastructure RF. In 2002, he joined Barcelona Design, Newark, CA. He is presently Director of Analog Synthesis Engine Development. His research interests include synthesis of data converters and phase-locked loops.

Author / Presenter: Lawrence Larson, UCSD
Publication Year: 2004

Abstract: SiGe BiCMOS technology has established a strong presence in the high-performance analog/RF communications-IC market. The wide range of device options, along with their outstanding high-frequency performance, make the technology a natural choice for high-performance low-dc-power applications. This presentation will summarize the key design advantages of SiGe, and highlight some particular applications where the use of SiGe bipolar devices with their high linearity, high transconductance, and high breakdown voltage can lead to substantial improvements in performance and dc power. Particular attention will be paid to emerging wireless applications like 3G and 802.11a.

Originally presented during the 2004 ISSCC Short Course, "Deep Submicron Analog/RF Circuit Design"
Presentations from this short course include:

• Models for Deep Sub-Micron Analog/Mixed-Signal ICs: 2004 ISSCC Short Course Segment
• Analog Circuit Design in Deep Sub-Micron CMOS Processes: 2004 ISSCC short Course Segment
• Recent Developments in RF CMOS Transceivers: 2004 ISSCC Short Course Segment
• Analog/RF Design in SiGe BiCMOS: 2004 ISSCC Short Course Segment

Author Bio: Lawrence Larson received the B.S. and M.Eng. degrees in Electrical Engineering from Cornell University, and the PhD from UCLA in 1986. He was at Hughes Research Laboratories from 1980 to 1996, where he worked on the development of InP, GaAs, CMOS, SiGe and MEMs- based devices and circuits for communications. Since 1996, he has been a Professor at UCSD, where he is currently Director of the UCSD Center for Wireless Communications. He is the co-recipient of a number of awards for his work on high-speed microelectronics, has coauthored three books, published over 200 paper, and has 27 US patents.

Author / Presenter: Marc Tiebout, Infineon Technologies Austria, Villach
Publication Year: 2007

Abstract: A general introduction covering system aspects of RF communication and relevant definitions, will be given. The tutorial covers CMOS RFIC design of low noise amplifiers LNAs and downconversion mixers. The circuit-design lecture first treats the modeling of CMOS devices including noise sources. Next, LNA and mixer design is presented from specifications to detailed topology discussions including all relevant aspects like impedance matching, noise figure, gain, bandwidth, linearity, and low-voltage design, without forgetting the crucial and critical RF ESD protection of LNAs. The circuits are illustrated through many measured test chip case studies aiming at RF standards from 1 to 20GHz. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Marc Tiebout (S'90-M'93) received his M.S. degree in electrical and mechanical engineering in 1992 from the Katholieke Universiteit Leuven (Belgium) and the Ph.D. degree in electrical engineering from the Technical University of Berlin in 2004. In 1993, he joined Siemens, Corporate Research and Development, Microelectronics, in Munich, Germany, designing analog integrated circuits in CMOS and BiCMOS technologies. In 1997 he started the design of RF devices and building blocks in sub-μm CMOS technologies. From 1999 to 2005, he was with Infineon Technologies AG, Munich, Germany, where he worked on RF CMOS circuits and transceivers for cellular wireless communication products and conducted high-frequency RF CMOS research for 17 and 24GHz applications. Since March 2006, he is with Infineon Technologies Austria, Villach, acting as concept engineer for UWB front-end development. His main interest focusses on low-power high-frequency circuits and systems in CMOS. Marc Tiebout serves as a member of the technical program committee of ISSCC and ESSCIRC. He has authored and coauthored more than 30 IEEE publications.

Author / Presenter: Yiannos Manoli, University in Duisburg
Publication Year: 2007

Abstract: While technologies are continuing to provide us with ever faster transistors they also demand that we work at lower supply voltages. The analog designer has to search for new concepts to counteract the reduction of signal swings and increase in power. Although time-continuous circuits are anything but new, they are gaining a renewed interest not only in the academic, but also in the industrial community. With the main focus on baseband applications, different aspects of continuoustime delta sigma modulators will be covered when operated under low-power and lowvoltage constraints:• Architectures for baseband applications • Implicit anti-aliasing filter • Influence of non-idealities and correction techniques • Implementations (low power, ultra wideband, high performance) one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Yiannos Manoli holds the Chair of Microelectronics at the University of Freiburg, Germany. His current research interests lie in the design of low-voltage and low-power mixed-signal CMOS circuits, sensor read-out circuits as well as A/D- and D/A-converters with over 150 papers in these areas. He holds a B.A. degree in Physics and Mathematics, a M.S. degree in electrical engineering and computer science from the University of California, Berkeley, and the Dr. Ing. Degree in electrical engineering from the Gerhard Mercator University in Duisburg, Germany.

Author / Presenter: Ron Ho
Publication Year: 2008

Abstract: This tutorial discusses on-chip wires, how to model them, what are their problems (and their advantages) and some solutions. Topics that will be covered include: Wire characteristics and how they determine performance; Wires under technology scaling; and Methods to improve wire performance.


Author Bio: Ron Ho is a Senior Research Scientist at Sun Microsystems Laboratories in Menlo Park, CA, where he worries about the future of wires. He received his Ph.D. in electrical engineering from Stanford University. From 1993 to 2003, he was at Intel in Santa Clara, CA, where he worked on processors ranging from the 80486 to the 3rd-generation Itanium. In 2003, he joined Sun Labs, where he is currently researching highperformance and low-energy communication technologies, both on a single chip and between two chips. In 2005, he was also a Lecturer at Stanford University, where he taught a graduate class on circuit design.

Author / Presenter: Richard Schreier
Publication Year: 2006

Abstract: Delta-sigma ADCs are the preferred architecture when dynamic-range requirements exceed 13 bits or so. This presentation will explore the most important properties of delta-sigma ADCs, including inherent linearity, and (for continuous-time systems) inherent anti-aliasing. These properties are illustrated in the context of the simplest delta-sigma ADC, the first-order modulator, and then generalized to second- and higher-order modulators. Then, bandpass modulation, quadrature modulation, cascade modulation, and mismatch-shaping, are introduced, and shown to fit into the same basic framework, namely that of high-gain linear feedback around a nonlinear element. Each of these delta-sigma variants is illustrated with examples constructed using the Delta-Sigma Toolbox.

Note: This presentation was presented within the 2006 ISSCC A/D Converters Short Course and included the following presentations:
- Sub-1V Analog-to-Digital Converters
- Fundamental Limits and Practical Design Issues in A/D Converters
- Pipelined A/D Converters
- Delta Sigma ADCs

Author Bio: Richard Schreier received his Ph.D. from the University of Toronto, in 1991. From 1985 to 1987, he worked at Bell-Northern Research in Ottawa, anada, and, from 1991 to 1997, he was an Assistant/Associate Professor at Oregon State University in Corvallis. Since 1997, he has been working for Analog Devices, Inc. in Wilmington, Massachusetts. In 2002, he received the ISSCC outstanding-paper award for a paper describing a 50mW bandpass delta-sigma ADC with 90dB of dynamic range, and 300kHz of bandwidth. He co-edited an IEEE Press book (with S.R. Norsworthy and G.C.Temes), published in 1997. His second book (with G.C. Temes) on delta-sigma modulation was published in 2004. He is also the author of the freeware Delta-Sigma Toolbox for MATLAB.

Author / Presenter: Kofi A. A. Makinwa, Delft University of Technology
Publication Year: 2007

Abstract: In analog CMOS design, offset is a fact of life! Even in modern processes, device mismatch typically results in offset voltages of several nV.millivolts. But many analog circuits, e.g. precision amplifiers, sensor interfaces, and ADCs require much lower offset levels. Fortunately, by using dynamic offset-cancellation techniques such as auto-zeroing and chopping, microvolt levels of offset can be routinely achieved in standard CMOS. Compared to the alternatives, i.e. the use of huge devices or trimming, the use of dynamic offset-cancellation techniques has the added advantage of also reducing 1/f noise and drift, thus making it possible to design circuits that are thermal-noise limited. In this tutorial, an introduction to the basic theory behind auto-zeroing and chopping will be given, the pros and cons of both techniques highlighted, and recent advances in the state-of-the-art reviewed. Examples will be given of the use of auto-zeroing and chopping in CMOS circuits and systems with residual offsets as low as 50nV. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Kofi A. A. Makinwa is an Associate Professor at Delft University of Technology, The Netherlands. He received the B.Sc. and M.Sc. degrees from Obafemi Awolowo University, Nigeria, in 1985 and 1988, respectively. In 1989, he received the M.E.E. degree from the Philips International Institute, The Netherlands, and then joined Philips Research Laboratories as a research scientist. In 2004, he received the Ph.D. degree from Delft University of Technology. He holds nine U.S. patents, has (co)-authored over 40 technical papers, and has given tutorials at the Eurosensors and the IEEE Sensors conferences. His main research interests are in the design of precision analog circuitry, ΔΣ modulators, and sensor interfaces. Dr. Makinwa has served on the technical program committees of the ISSCC, the International Solid-State Sensors and Actuators Conference (Transducers), and the IEEE Sensors conference. In 2005, he received the Veni and Simon Stevin Gezel awards from the Dutch Technology Foundation (STW), and was a co-recipient of the ISSCC 2005 Jack Kilby award.

Author / Presenter: Kenneth O, University of Florida, Gainesville
Publication Year: 2005

Abstract: Silicon-based technologies use substrates with resistivities ranging between 0.01 and ~20Ω-cm. This relatively low substrate resistivity, if not properly engineered, can significantly degrade characteristics of transistors, inductors, capacitors, interconnects as well as the performance of LNAs, VCOs, mixers, transmit/receive switches, and power amplifiers. In general, the degradation can be minimized by making the substrate resistance either very small or very large. For silicon integrated circuits, it is more practical to lower the substrate resistances. However, lowering the substrate resistances can degrade amplifier stability, and increase unwanted noise and signal coupling. The underlying mechanisms for these are presented. With the increase of operating frequencies of RFCMOS circuits, integration of antennas has become a realistic option. The effects of substrate on on-chip antenna performance are also described.

Note: This presentation was presented within the 2005 ISSCC Short Course: RF Circuit Design-Technology to Systems and included the following presentations:
- Technology Options for RF-ICs
- Wireless IC Building Blocks in CMOS/BiCMOS
- Effects of Substrate on the RF Performance of Silicon Integrated Circuits
- Front-End Design for Wireless Systems

Author Bio: Kenneth O received his S.B, S.M, and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. From 1989 to 1994, he worked at Analog Devices developing CMOS, bipolar, and BiCMOS processes for RF and mixed signal applications. He is currently a professor at the University of Florida, Gainesville. His research group is developing circuits and components operating between 1 and 100GHz using silicon IC technologies. He was the general chair of the 2001 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. He has authored and co-authored approximately 100 publications and holds five patents.

Author / Presenter: Philip K.T. Mok, Hong Kong University of Science and Technology
Publication Year: 2007

Abstract
Due to the drastic increase of system integration and power consumption of an IC with technology scaling, power management becomes a critical issue in determining the overall performance of the IC. This tutorial starts with a brief overview of power management circuits for embedded applications. There follows a detailed explanation of the operation and design issues associated with various on-chip power converter circuits including linear regulator, switched-inductor regulator, and switched-capacitor regulator. The focus is on the analog circuit techniques, and the control mechanism for implementing these power converters. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Philip K.T. Mok received his B.A.Sc., M.A.Sc., and Ph.D. degrees in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada, in 1986, 1989, and 1995, respectively. In January 1995, he joined the Department of Electronic and Computer Engineering at the Hong Kong University of Science and Technology, Hong Kong, China, where he is currently an Associate Professor. His current research interests include power-management integrated circuits and low-voltage analog integratedcircuits. He received the Henry G. Acres Medal, the W.S. Wilson Medal, and a Teaching-Assistant Award from the University of Toronto, and the Teaching Excellence Appreciation Award twice from The Hong Kong University of Science and Technology. He has served on the ISSCC analog sub-committee since 2005 and is an associate editor for the IEEE Transactions on Circuits and Systems II and the Journal of Solid-State Circuits since 2006.

Author / Presenter: Takayuki Kawahara
Publication Year: 2007

Abstract: Today's memories are increasingly susceptible to cosmic-ray-induced errors. In addition, lowering the supply voltage can increase circuit errors by reducing noise margin. Error-correcting code (ECC) can help solve both these problems by adding redundancy that allows recovery from errors. This tutorial starts from the basics of Shannon's theorem, and explores the need of ECC in nano-scale CMOS, soft errors in memory and basic coding such as Hamming code, cyclic code, and BCH code. It covers these topics in the context of modern memory, and their effect in advancing memory performance. The techniques are also applicable to high-speed logic. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English


Author Bio: Takayuki Kawahara is a chief researcher at Central Research Laboratory, Hitachi Ltd. Since joining the laboratory in 1985, he has made fundamental contributions in many areas in the field of low-power memories, including subthreshold-current reduction by gate-source self-reverse biasing, an over-drive sense-amplifier scheme, and charge-recycling. Currently, his responsibility is to explore a new conceptual memory. He received B.S. and M.S. degrees in physics in 1983 and 1985, and a Ph.D. degree in electronics in 1993 from Kyushu University, Fukuoka, Japan.

Author / Presenter: Robert Bogdan Staszewski, Texas Instruments
Publication Year: 2007

Abstract
Frequency synthesizers are currently an integral part of digital, mixed-signal, and RF system-on-chip solutions. As CMOS processes scale down, raw transistor performance and power consumption dramatically improve on the one hand, but difficulties arise in implementing traditional phase-locked loop architectures on the other hand. In this presentation Robert Bogdan Staszewski will first review these challenges — low-voltage limitations, high gate and off-channel leakage, high flicker noise, highly nonlinear device characteristics, poor isolation from digital logic — and will then summarize some well-known workarounds. He will then focus on recently developed solutions that are usable in nanometer CMOS processes.

Note: This presentation was presented within the 2007 ISSCC Short Course: Analog, Mixed Signal and RF Circuit Design in Nanometer CMOS. The full list of presentations included in that short course is provided here for your reference:

* RF Transceiver System Design in Nanometer CMOS
* RF Circuit Design in Nanometer CMOS
* Frequency Synthesizers in Nanometer CMOS
* Continuous-Time ADCs in Nanometer CMOS

Author Bio: Robert Bogdan Staszewski received his Ph.D. from the University of Texas at Dallas in 2002 for his research on RF frequency synthesis in digital deep-submicron CMOS. From 1991 to 1995, he worked at Alcatel Network Systems in Richardson, TX. He joined Texas Instruments in Dallas, TX, in 1995 where he holds an elected title of Distinguished Member of Technical Staff for his pioneering work on the Digital RF Processor (DRP) architecture. He is currently a manager of DRP system and design development for transmitters and frequency synthesizers. He has authored and co-authored 60 journal and conference publications and holds 30 issued and 35 pending US patents.

Author / Presenter: Ranjit Gharpurey, University of Michigan
Publication Year: 2005

Abstract: Design techniques relevant to RF front-ends and transceivers for wireless applications are discussed in the course. Considerations such as noise and linearity performance, dynamic range, matching and parasitic self-induced noise in these circuits are addressed. The discussion includes techniques applicable to traditional narrow-band and recently emerging broad-band wireless systems, such as Ultra Wideband. A comparison of design issues and trade-offs for the two types of systems is also presented.

Note: This presentation was presented within the 2005 ISSCC Short Course: RF Circuit Design-Technology to Systems and included the following presentations:
- Technology Options for RF-ICs
- Wireless IC Building Blocks in CMOS/BiCMOS
- Effects of Substrate on the RF Performance of Silicon Integrated Circuits
- Front-End Design for Wireless Systems

Author Bio: Ranjit Gharpurey is an Assistant Professor in the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. His primary research interests are in the areas of high-frequency and high-speed circuit design and parasitic noise sources in integrated circuits with emphasis on RFIC design for wireless applications. He received his Ph. D. from the University of California at Berkeley in 1995 and his B. Tech from the Indian Institute of Technology, Kharagpur.

Author / Presenter: Hae-Seung Lee, MIT
Publication Year: 2006

Abstract: In this presentation, fundamental limitations of ADCs associated with noise, clock jitter, power consumption, and conversion rate, are discussed. Figures-of-merit (FoM) based on these fundamental limits will be compared in various ADC topologies including flash, pipeline, successive-approximation, and ΔΣ converters. Design strategies for improving FoMs in practical ADCs will also be discussed. Finally, practical design issues, such as component mismatch, finite-gain effects, charge injection, and substrate noise with techniques for reducing its effects, will be described.

Note: This presentation was presented within the 2006 ISSCC A/D Converters Short Course and included the following presentations:
- Sub-1V Analog-to-Digital Converters
- Fundamental Limits and Practical Design Issues in A/D Converters
- Pipelined A/D Converters
- Delta Sigma ADCs

Author Bio: Hae-Seung Lee received his Ph.D. from the University of California, Berkeley, in 1984, where he pioneered self-calibration techniques for A/D converters. In 1984, he joined the faculty at the Massachusetts Institute of Technology, Cambridge, MA, where he is now Professor and Director of the Center for Integrated Circuits and Systems. Since 1985, he has acted as a consultant to Analog Devices, Lincoln Laboratories, and Cypress Semiconductor. He has authored or co-authored more than 100 journal and conference papers. He is a Fellow of the IEEE.

Author / Presenter: Naresh Shanbhag, Intersymbol Communications
Publication Year: 2007

Abstract: Electronic dispersion compensation (EDC) has emerged as the technology enabling the migration of metro and long-haul optical fiber and backplane links to 10Gb/s to 40Gb/s rates. Both links suffer from various forms of dispersion or intersymbol interference (ISI), and noise. Fiber links also exhibit non-linearities due to fiber amplifiers and the photo-detector. The stringent power and throughput requirements have forced transmit and receiver ICs to be predominantly mixed-signal and the modulation to be binary. Meeting the challenges of designing next generation high data rate systems within a tight power budget requires the designer to understand the very basis of information transfer and go beyond the waveform shaping aspect exemplified by the ‘eyeopening’ techniques prevalent today. This tutorial will provide an overview of efficient transmit and receive techniques for both linear (back-plane) and nonlinear (fiber) channels such as matched filtering, linear, decision-feedback, transmit techniques (pre-emphasis and partial response coding), maximum likelihood detector (‘Viterbi equalizer’) and their implications on mixed-signal design. The design of an OC-192 EDC chip-set will be presented as a case-study. Finally, the tutorial will conclude with a discussion on advanced topics and future directions. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Naresh Shanbhag is currently a Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign, Urbana, IL, USA. His research interests are in the area of low-power/high-performance integrated circuits and systems for DSP and communications. He is also a co-founder and Chief Technology Officer of Intersymbol Communications, Inc., (a wholly owned subsidiary of Kodeos Communications, Inc., since March 2006) Champaign, IL, USA, which was founded in 2000, and where he provides strategic directions in the development of EDC based mixed-signal receivers for next generation optical fiber links. He received his Ph.D. in EE from the University of Minnesota, located in Minneapolis, USA, in 1993. From 1993, Dr. Shanbhag worked at AT&T Bell Laboratories where he lead the development of its 51.84Mb/s VDSL chip-sets before joining the University of Illinois in 1995. Dr. Shanbhag became an IEEE Fellow in 2006, received the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society. From 1997 to 1999 and from 1999 to 2002, he served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II and the IEEE Transactions on VLSI, respectively.

Author / Presenter: Takayasu Sakurai, University of Tokyo
Publication Year: 2007

Abstract: Organic transistors are expected to provide a way to build printable, flexible, and large-area electronic systems, which may open up new applications. This tutorial provides a comprehensive view of integrated circuit design approaches based on organic transistors. The tutorial covers organic IC examples like E-skin, sheet-type scanner, and Braille display. • Technology aspect (process, structure, material, and encapsulation) • Advantages and disadvantages • Circuit design (modeling, and what are the differences from silicon) • Coping with issues of low speed and reliability • Applications and design examples • Remaining issues and future directions. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Takayasu Sakurai received the B.S., M.S. and Ph.D degrees in electrical engineering from University of Tokyo. In 1981, he joined Toshiba, where he designed numerous VLSI products including memories and processors. From 1988 to 1990, he was a visiting researcher at University of California, Berkeley. From 1996, he is a Professor at University of Tokyo, working on VLSI design and organic circuits. He was a conference chair and a TPC member of international conferences in the field of VLSI design including ISSCC, VLSI Circuit Symp., A-SSCC, CICC, ESSCIRC, and DAC. He is a recepient of 2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award, 2005 P&I patent of the year award, and other awards. He is an IEEE Fellow, a STARC Fellow, an elected AdCom member for the IEEE SSCS, and an IEEE CAS and SSCS distinguished lecturer.

Author / Presenter: Bang-Sup Song, UCSD
Publication Year: 2006

Abstract: As CMOS processes scale down, ADC designers benefit greatly from both device speed and lithographic accuracy: Device speed contributes directly to the prevailing trend toward oversampling techniques in high-resolution ADC designs. On the other hand, finer-line feature size offers better component matching for a fixed device size, and Nyquist-rate pipelined techniques still provide power- and area-efficient solutions for high-speed medium-resolution applications. Correspondingly, advanced pipelined ADC techniques have been further developed to enhance resolution. This presentation begins by identifying the fundamental limits in achieving accuracy and speed with basic pipelining techniques. It will then focus on design issues related to high speed and high resolution.

Note: This presentation was presented within the 2006 ISSCC A/D Converters Short Course and included the following presentations:
- Sub-1V Analog-to-Digital Converters
- Fundamental Limits and Practical Design Issues in A/D Converters
- Pipelined A/D Converters
- Delta Sigma ADCs

Author Bio: Bang-Sup Song received his Ph.D. from the University of California, Berkeley, in 1983. He was with AT&T Bell aboratories, urray Hill, and the ECE Department, University of Illinois, Urbana-Champaign, before he joined the ECE Department, University of California, San Diego, in 1999, where he is endowed as the Charles Lee Powell Chair Professor in Wireless Communication. His current interest is in CMOS analog circuits including data converters, wireless ransceivers, TV tuners, frequency synthesizers, image-rejection techniques, active filters, and timing recovery. His research has been focused on improving analog-circuit performance using digital aids. He is an IEEE Fellow.

Author / Presenter: Arya Behzad, Broadcom
Publication Year: 2007

Abstract: Essential to the overall system design of a MIMO system, is the radio design. This course will provide a brief introduction to the legacy 802.11 a/b/g systems, followed by a discussion of the history of multiple antenna systems and the conventional analog-based techniques such as MRC. A general introduction to the 802.11n will then follow, which includes the channelization and modulation types, the definition and the description of the concepts behind the multiple spatial streams (MxN), and additional PHY and MAC techniques allowing for higher rates and/or longer reach. These features include the use of short guard-interval (GI), implicit and explicit beam-forming, space-time block codes (STBC), the use of Greenfield mode, and aggregation techniques. The requirements of 802.11n standard such as sensitivity and EVM and their relation to analog impairments such as phase noise, quadrature imbalances, linearity, and cross-talk will also be discussed. Some specific circuit examples will be presented and some unique circuit implementation challenges of MIMO radios will be discussed. Some measured performance numbers (range and throughput) will be also presented. The course will wrap up by discussing the future trends of MIMO radio implementation. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Arya Behzad has worked in various senior circuit and system design capacities at various companies. Since 1998 he has been with Broadcom Corporation working on integrated tuners, gigabit Ethernet and wireless LAN systems and ICs. He is currently a Director of Engineering working on radios for current and future generation wireless products, and Product Line Manager for all Wireless LAN Radio products. He has over 70 patents issued and pending as well as many publications in the areas of precision analog circuits, cellular transceivers, integrated tuners, gigabit Ethernet, and wireless LANs. He has taught courses and presented technical seminars at various conferences and at several universities. Mr. Behzad is on his fifth year serving as a member of the ISSCC Wireless Technical Committee. He has served as a Guest Editor of JSSC and is currently an Associate Editor of the Journal. Mr. Behzad obtained his M.S. EE from UC Berkeley in 1994 after completing his thesis on the Infopad project.

Author / Presenter: Behzad Razavi, UCLA
Publication Year: 2004

Abstract: This presentation describes new RF architectures and circuit techniques developed for highperformance wireless communications. Design techniques for zero-IF, low-IF, single-VCO heterodyne, and offset-PLL architectures are presented, and examples of the state-of-the-art for various wireless standards are reviewed. RF circuit topologies that alleviate architecture issues, and lend themselves to realization in CMOS are also described, and comparative studies of recently-reported transceiver designs, in the range of 1 to 5 GHz are used to illustrate issues and trade-offs.

Originally presented during the 2005 ISSCC Short Course, "Deep Submicron Analog/RF Circuit Design"
Presentations from this short course include:

• Models for Deep Sub-Micron Analog/Mixed-Signal ICs: 2004 ISSCC Short Course Segment
• Analog Circuit Design in Deep Sub-Micron CMOS Processes: 2004 ISSCC short Course Segment
• Recent Developments in RF CMOS Transceivers: 2004 ISSCC Short Course Segment
• Analog/RF Design in SiGe BiCMOS: 2004 ISSCC Short Course Segment

Author Bio: Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on high-speed data communication circuits, wireless transceivers, phase-locking phenomena, and data converters. He is an IEEE Distinguished Lecturer, a Fellow of IEEE, and recipient of numerous awards at ISSCC, ESSCIRC, and CICC. He was also recognized as one of the top 10 authors in the 50-year history of ISSCC. He has published six books in the area of analog and RF design, two of which have been translated to Chinese and Japanese.

Abstract
With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and non-quadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern multi-band communication systems as these systems move toward software-defined radio. These trends in technology and system design call for a re-thinking of analog and RF circuit design in nanometer CMOS. Bram Nauta will discuss innovations intended to enable continued progress in spite of these challenges. These innovations include thermal noise canceling, poly-phase distortion canceling and 1/f noise reduction techniques applied to basic RF circuits.

Note: This presentation was presented within the 2007 ISSCC Short Course: Analog, Mixed Signal and RF Circuit Design in Nanometer CMOS. The full list of presentations included in that short course is provided here for your reference:

* RF Transceiver System Design in Nanometer CMOS
* RF Circuit Design in Nanometer CMOS
* Frequency Synthesizers in Nanometer CMOS
* Continuous-Time ADCs in Nanometer CMOS


Author Bio: Bram Nauta received the M.Sc degree (cum laude) in Electrical Engineering from the University of Twente, Enschede, The Netherlands in 1987. In 1991 he received the Ph.D. degree from the same university on the subject of analog CMOS filters for very high frequencies. In 1991 he joined the Mixed-Signal Circuits and Systems Department of Philips Research, Eindhoven the Netherlands, where he worked on high-speed AD converters. From 1994 to 1998 he led a research group in the same department working on "analog key modules." In 1998 he returned to the University of Twente, as full professor heading the IC Design group, which is part of the CTIT Research Institute. His current research interest is high-speed analog CMOS circuits.

Author / Presenter: Matt Miller, Freescale Semiconductor
Publication Year: 2007

Abstract
In articles, textbooks and research papers we are told again and again that even as CMOS gate lengths become ever smaller, "the analog doesn't shrink." But cell phones have gotten smaller somehow, and the smart money says they will continue to pack more features in the same or smaller form factor for some time to come. Many of the secrets behind this apparent contradiction lie in the IC systemlevel design. The RF transceiver designer is faced with myriad design choices that have huge impacts on the overall IC performance. Simply choosing the performance targets for the IC is not to be taken lightly. For example, just as in the digital and traditional mixedsignal domains, a goal of minimizing die area as opposed to minimizing current draw can lead to a vastly different set of choices for the LNA, Mixer, baseband filter, and data converter parameters. Likewise, those ever-shrinking gate lengths do indeed lead one to make sharp turns along the path toward the final block specifications. In this presentation Matt Miller will briefly review the history of transceiver design, which has brought us to the present situation wherein the inclusion of an all-CMOS transceiver in a handheld phone is fast becoming the norm. He will then examine the changes in the CMOS environment - the side effects of all those shrinking gates - that are driving the trend toward digitally assisted and sometimes even disappearing analog circuits, and will show examples of how this trend is making itself felt in the RF arena.

Note: This presentation was presented within the 2007 ISSCC Short Course: Analog, Mixed Signal and RF Circuit Design in Nanometer CMOS. The full list of presentations included in that short course is provided here for your reference:

• RF Transceiver System Design in Nanometer CMOS
• RF Circuit Design in Nanometer CMOS
• Frequency Synthesizers in Nanometer CMOS
• Continuous-Time ADCs in Nanometer CMOS

Author Bio
Matt Miller received the B.S. degree in electrical engineering from Purdue University in West Lafayette, Indiana in 1987 and the M.S. degree in electrical engineering from National Technological University in 1996. He joined Motorola in 1988 as a member of the Secure Communications Division where he worked on the development of custom integrated circuits for use in encrypted voice radio products. In 1994, he joined Motorola’s Communications Research Labs and since that time has been involved in the research and design of mixed-signal and RF integrated circuits with emphasis on data conversion and RF transceivers. He is currently a Distinguished Member of the Technical Staff in the Advanced Technology Group of Freescale Semiconductor. He holds 13 patents, has two patents pending, and is the co-author of five IEEE papers and one AES paper.

Author / Presenter: Un-Ku Moon, Oregon State University
Publication Year: 2006

Abstract: The analog-to-digital converter is an important analog-interface circuit-block. However, it is becoming a critical bottleneck in mixedsignal IC systems, as CMOS-transistor dimensions shrink in state-of-the-art technology. This is due to the fact that transistors of smaller dimensions can tolerate only a proportionally smaller voltage stress. This presentation will review the low-voltage problem, summarize some of the well-known solutions currently in use (and their associated problems), and introduce recently-developed circuit techniques. A few IC-implementation results for both oversampling and Nyquist analog-to-digital converters which operate below 1V will be presented as possible design solutions for future low-voltage submicron CMOS processes.

Note: This presentation was presented within the 2006 ISSCC A/D Converters Short Course and included the following presentations:
- Sub-1V Analog-to-Digital Converters
- Fundamental Limits and Practical Design Issues in A/D Converters
- Pipelined A/D Converters
- Delta Sigma ADCs

Author Bio: Un-Ku Moon received his B.S. from the University of Washington, his M.Eng. from Cornell University, and his Ph.D. from the University of Illinois, Urbana-Champaign, all in electrical engineering. He has been with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, since 1998, where he is currently an Associate Professor. Before joining Oregon State University, he was with Bell Laboratories from 1994 to 1998, as well as from 1988 to 1989. His research interests include highly-linear and tunable continuous-time filters, telecommunication circuits including timing-recovery and data-converters, and ultra-low-voltage analog circuits.

Author / Presenter: S. Simon Wong, Stanford
Publication Year: 2005

Abstract: The focus of this presentation is to review the various technology options for RF integrated circuits; CMOS versus BiCMOS, MIM capacitors, varactors, inductors, switches, triple well isolation, ESD protection and packages.

Note: This presentation was presented within the 2005 ISSCC Short Course: RF Circuit Design-Technology to Systems and included the following presentations:
- Technology Options for RF-ICs
- Wireless IC Building Blocks in CMOS/BiCMOS
- Effects of Substrate on the RF Performance of Silicon Integrated Circuits
- Front-End Design for Wireless Systems

Author Bio: S. Simon Wong received the MS and PhD degrees from the University of California at Berkeley. He worked at National Semiconductor, Hewlett Packard Laboratories, and Cornell University. In 1988, he joined Stanford University where he is now a Professor of Electrical Engineering. His research group focuses on understanding and overcoming the limitations of circuit performance imposed by device, interconnection and on-chip components. He is a Fellow of the IEEE.

Author / Presenter: Kees van Berkel, NXP Research in Eindhoven
Publication Year: 2007

Abstract: Wireless radio standards (for cellular, broadcast, connectivity, and positioning) are rapidly proliferating and continuously evolving. Accordingly, the trend in mobile handsets is toward multi-standard and multi-channel solutions (short term), and software defined radio (SDR) and cognitive radio (long term). The required baseband signal processing involves many giga operations per second, at a power budget of only a few hundred mW. In this tutorial we analyze the trade-off between the required flexibility (programmability) versus power consumption and die area for SDR. For a large class of baseband functions (including demodulation, channel estimation, equalization, interference cancellation, synchronization), programmable vector processing (SIMD) is presented as a key enabler for SDR. A number of vector processors are reviewed, ranging from products today to academic prototypes. one of TEN bundled 90-minute Tutorials, with audio, visuals, and transcription of the audio in English.

Author Bio: Kees van Berkel is a Fellow at NXP Research in Eindhoven, the Netherlands. He received an M.S. degree (cum laude) in electrical engineering at the Delft University of Technology in 1980 and a PhD degree in computer science from the Eindhoven University of Technology (TU/e, 1992). Since 1996, he is a visiting Professor at the TU/e. During the 90s, he pioneered research on asynchronous VLSI circuits and contributed to their industrial application. Since the late 90s, his research focus moved to architectures for mobile wireless terminals. He initiated and co-architected the EVP, NXP's vector processor for modem applications. His current research interests include software-defined radio, signal processing algorithms, low-power vector DSPs, and interconnect-centric device architectures.

Author / Presenter: John Long, Delft U of Technology
Publication Year: 2005

Abstract: The design of wireless RF IC building blocks, such as low-noise amplifiers (LNA), up and down-converting mixers and VCOs are described in this lecture. Both low-voltage/low-current and high-performance aspects of RF design are treated. The limitations and advantages of on-chip passive components in RF circuits - important to VCOs and low-voltage circuits among others - are included. Modelling, optimization and physical layout of passives for different circuit applications are described. Design examples in both CMOS and BiCMOS for single-chip (e.g., Bluetooth, 802.11x) and multi-standard transceivers are presented.

Note: This presentation was presented within the 2005 ISSCC Short Course: RF Circuit Design-Technology to Systems and included the following presentations:
- Technology Options for RF-ICs
- Wireless IC Building Blocks in CMOS/BiCMOS
- Effects of Substrate on the RF Performance of Silicon Integrated Circuits
- Front-End Design for Wireless Systems

Author Bio: John Long received the MEng and PhD degrees in Electronics from Carleton University in 1992 and 1996, respectively. He worked for 10 years at Bell-Northern Research on Gb/s fiber systems, and for 5 years at the University of Toronto. He joined Delft University of Technology in 2002 as Chair of the Electronics Research Laboratory, and currently serves on the ISSCC, ESSCIRC, BCTM, and European Microwave conference committees. His current research interests include: low-power transceiver circuitry for broadband and highly integrated radios, and electronics for high-speed data communications systems.